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FIN1002-FIN1002,LVDS 1-Bit High Speed Differential Receiver

General Description
This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data.
The FIN1002 can be paired with its companion driver, the FIN1001, or with any other LVDS driver.
 Greater than 400Mbs data rate
 3.3V power supply operation
 0.4ns maximum pulse skew
 2.5ns maximum propagation delay
 Bus pin ESD (HBM) protection exceeds 10kV
 Power-Off over voltage tolerant input and output
 Fail safe protection for open-circuit and non-driven, shorted or terminated conditions
 High impedance output at VCC < 1.5V
 Meets or exceeds the TIA/EIA-644 LVDS standard
 5-Lead SOT23 package saves space


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